This invention relates to an integrated circuit carrier and testing fixture. More particularly, this invention relates to an improved carrier which permits the integrated circuit or semiconductor chip to be inspected and tested both electrically and environmentally with a minimum of direct handling while protecting the chip against damage.
Typically, a plurality of identical semiconductor chips are formed on a wafer where they can be subjected to limited tests. After these tests, the chips, which are typically about a sixteenth of an inch square, are separated and then each chip is mounted in an integrated circuit package. The package, in turn, can be mounted in a carrier, such as shown in Barnes U.S. Pat. No. 3,409,861, and then tested and inspected by conventional methods set forth in that patent.
In many applications it is desirable to reduce the size of the electronic equipment. It also is important to reduce the weight of electronic equipment as well as other devices used in satellites and the like. One technique is to not mount the semiconductor chip in an IC package, but to mount it directly to a hybrid circuit. However, due to the inordinately small size of the semiconductor chip it is not possible to perform a number of tests on it.
Attempts have been made to develop a carrier and holding fixture for the uncased semiconductor chip that would allow the semi-conductor chip to be subjected to electrical and environmental testing as well as a short period of actual operation, commonly referred to as "burn-in". See U.S. Pat. No. 3,823,350. One problem is the beam leads on the semiconductor chip, being made up of gold deposited over platinum, tend to weld themselves to the gold plated copper leads on the carrier. Another problem is that the prior carriers, since they contain a plastic cover that springs against a semiconductor chip to hold the chip in position, cannot be used at elevated temperature within the desirable range because the plastic loses its resiliency at the higher temperature which can allow the chip to move, thus subjecting the semiconductor chip to possible damage and possible loss of electrical contact to the chip.
Still another problem inherent in the prior art carriers is that the non-uniformity of size of the various pieces due to manufacturing tolerances allows the beam leads on the chip to contact more than one conductor, or no conductors, whereby the chip can be damaged when power is applied. Specifically, in the prior art carriers, the printed circuit board or other device supporting the conductive traces must be lined up with the base of the carrier. In turn, the cover, which determines the position of the semiconductor chip, also must be lined up with the base of the carrier. Since the beam leads from the carrier are only approximately 5 mils (0.005 inches) wide and the beam leads are spaced apart by approximately 5 mils, any misalignment of the chip carrier base with the printed circuit board or the cover can cause the chip to not make a proper connection with the copper traces and the application of current could destroy the chip.
Yet another problem is that the chip can be easily damaged when it is being loaded or unloaded from the carrier. The beam leads of the semiconductor chip are so small and delicate that they can be damaged by the slightest sliding of them across the supporting printed circuit board. Thus, any sliding movement of the cover along the printed circuit should be avoided.